The present invention relates to ferromagnetic thin film memories and, more particularly, to ferromagnetic thin film memories in which states of the memory cells based on magnetization direction are determined through magnetoresistive properties of the thin film sensed by an electronic circuit.
Digital memories of various kinds are used extensively in computers and computer system components, in digital processing systems, and the like. Such memories can be formed, to considerable advantage, based on the storage of digital bits as alternative states of magnetization in magnetic materials in each memory cell, typically thin film materials. These films may be ferromagnetic thin films having information stored therein through the direction of the magnetization occurring in that film, with this information being obtained through either inductive sensing to determine the magnetization state, or by magnetoresistive sensing of such states. Such ferromagnetic thin film memories may be conveniently provided on the surface of a monolithic integrated circuit to provide easy electrical interconnection between the memory cells and the memory operating circuitry.
Ferromagnetic thin film memory cells can be made very small and packed very closely together to achieve a significant density of stored digital bits, properties which permit them to be provided on the surface of a monolithic integrated circuit as indicated above. One construction, as an example, is shown in FIG. 1, where a bit structure 10 for a memory cell that is presented is formed over a semiconductor material body 12, as used in a monolithic integrated circuit, and directly on an insulating layer 13, itself supported on a major surface of body 12 in the integrated circuit. Only a small portion of the integrated circuit is shown, and then only a small portion of the semiconductor body is shown in that integrated circuit portion.
These bit structures in an assemblage in a memory are usually provided in a series string of such bit structures often called sense lines. There are typically a plurality of such sense lines in a memory. In order to make interconnections between members of such sense lines, or between the sense lines and the external circuitry in the integrated circuit for operating the memory, terminal regions or junctures 14 are typically provided at each end of the bit structure for interconnection purposes. These interconnections might be formed of copper alloyed in aluminum.
The remainder of the bit structure disposed on the exposed major surface of insulating layer 13 includes a lower ferromagnetic thin film 15 and an upper ferromagnetic thin film 16. Ferromagnetic thin film layers 15 and 16 typically exhibit uniaxial anisotropy, magnetoresistance, little magnetostriction, and are of an alloy composition typically comprising nickel, cobalt and iron. The magnetic device structure can be a spin valve that includes a pinned reference layer 15 spaced apart from a xe2x80x9cfree layerxe2x80x9d that stores the digital information. The lower ferromagnetic thin film 15 is typically, but not always, thicker than the upper ferromagnetic thin film 16. Alternatively, a pseudo-spin-valve structure can be used where the lower ferromagnetic thin film 15 is often called the hard layer, and the upper ferromagnetic thin film 16 is often called the soft layer.
Between ferromagnetic thin film layers 15 and 16 is typically a further thin layer 17 which usually would not exhibit ferromagnetism but may be either an electrical conductor or an electrical insulator. Layer 17 must, however, in this construction, minimize the exchange interaction between layers 15 and 16 so that the magnetization vectors of each layer are decoupled. A typical choice for layer 17 would be copper. An insulating layer 18 covers bit structure 10 although only a part of it is shown in FIG. 1.
Finally, a word line 19 is shown in FIG. 1 disposed on the major surface of insulating layer 18. Word line 19 typically includes an aluminum layer alloyed with copper on a titanium-tungsten base layer. A protective and insulating layer over the entire structure of FIG. 1 is often used in practice, but is not shown here.
Bit structure 10 can be operated in a longitudinal mode having its easy axis extend between internal interconnections 14 perpendicular to the direction of word line 19. Information kept as a digital bit having one of two alternative logic values in bit structure 10 is stored therein in layer 15 by having the magnetization vector point in one direction or the other, generally along the easy axis of magnetization. If the direction of magnetization is caused to rotate from such a direction by external magnetic fields, the electrical resistance of layers 15 and 16 changes with this magnetization direction rotation because of the magnetoresistive properties of such layers. For the kinds of materials typically used in layers 15 and 16, the maximum change in resistance is on the order of a few percent of the minimum resistance value.
Sense current refers to the current flow through bit structure 10 from one terminal 14 to the other terminal 14 thereof, and word current refers to current flowing in word line 19 adjacent to, and transverse to the orientation of, bit structure 10. Bit structure 10 can be placed in one of the two possible magnetization states of layer 15 (pinned layer) through the selective application of sense and word currents i.e., information can be xe2x80x9cwrittenxe2x80x9d in bit structure 10. A bit structure 10 of a typical configuration can be placed in a xe2x80x9c0xe2x80x9d magnetization state by the application of a sense current of typically 1.0 mA, and coincidentally with the provision of a word current in one direction from 20 mA to 40 mA. The opposite magnetization state representing a xe2x80x9c1xe2x80x9d logic value can be provided through providing the same sense current and a word current of the same magnitude in the opposite direction. Such states typically occur fairly quickly after the proper current levels are reached, such state changes typically occurring in less than about 5 ns.
Determining which magnetization state is stored in bit structure 10 i.e., reading the information stored in bit structure 10, is typically done by providing externally caused magnetic fields in that bit structure, through providing, for example, wordline currents and sometimes coincident sense line currents. These currents rotate the magnetization of the upper ferromagnetic thin film 16 (free layer) of the bit structure 10, but preferably not the lower ferromagnetic thin film 15 (pinned layer). As indicated above, this causes a change in the electrical resistance encountered between terminal regions 14 in bit structure 10 for different magnetization directions in the structure, including changing from one easy axis direction magnetization state to the opposite direction state. As a result, there is detectable differences in the voltage developed across magnetic bit structure 10 by the sense current flowing therethrough, depending on the relative magnetization direction of the pinned and free layers of bit structure 10.
As the size of the bit structure 10 decreases, the magnetic field required to rotate the upper ferromagnetic thin film 16 and the lower ferromagnetic thin film 15 also tend to increase. Accordingly, the magnitude of the word line currents and sense lines currents increase. Depending on the technology used, this may cause the electro-migration limits of the metal interconnect layers to be exceeded. To help compensate for this, a digital line is sometimes provided over the bit structure 10 parallel with the sense line. The digital line provides an additional metal layer for carrying the required current, and provides additional lateral torque at the bit structure 10.
A limitation of many prior art magneto-resistive memories is that both sense lines and word lines are separately provided. Each of the sense lines and word lines typically requires a separate and often relatively large driver, which can result in significant peripheral overhead. This peripheral overhead often decreases the overall density of the memory and increases the overall power, both of which are undesirable.
The present invention overcomes many of the disadvantages of the prior art by providing a magneto-resistive memory that has a shared word line and sense line. By providing a shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents may be reduced. This may reduce the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.
In accordance with one illustrative embodiment of the present invention, a word line is provided adjacent a magneto-resistive bit. Rather than providing a separate sense line that interconnects the bit ends of the magneto-resistive bit to adjacent bits, one end of the magneto-resistive bit is connected to the word line and the other end is connected to a predetermined voltage such as ground through a switch or the like. The switch, which is preferably a transistor, selectively provides a path for a sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage. Accordingly, the word line may deliver both the word line current and the sense line current for the magneto-resistive bit. As such, no separate sense line current driver is required. Instead, a relatively small buffer or the like may be used to activate the switch, which then draws the sense line current from the word line.
Preferably, the magneto-resistive bit is elongated and has a length and a width. The magnetization vector of the pinned layer of the magneto-resistive bit preferably remains in a predetermined direction. Thus, the magneto-resistive bit may be written to a desired magneto-resistive state by changing the magnetization vector of only the free layer. The word line carries a word line current that produces a word line magnetic field component along the length of the elongated magneto-resistive bit. The word line magnetic field component provides the longitudinal force for switching the magnetization vector of the free layer of the magneto-resistive bit. The sense current, which passes through at least part of the magneto-resistive bit, preferably produces a sense magnetic field component that extends along the width of the elongated magneto-resistive bit. The sense magnetic field component provides the lateral torque sometimes necessary to initiate the rotation of the magnetization vector of the free layer of the magneto-resistive bit. A digital line may also be provided adjacent the magneto-resistive bit to provide additional lateral torque, if desired.
During a write operation, a word line current is provided to the word line, and the switch is activated. The switch draws a write sense current from the word line and through the magneto-resistive bit. The magnetic fields produced by the word line current and the write sense current are preferably sufficient to write the free layer of the magneto-resistive bit to the desired magneto-resistive state.
During a read operation, a word line current is not provided. Instead, a read circuit provides a path for a read sense current to flow to the word line. The switch is again activated, which draws the read sense current through the magneto-resistive bit. The read circuit senses the resistive state of the magneto-resistive bit by sensing the magnitude of the read sense current or by sensing the voltage drop across the magneto-resistive bit.
During a write operation, it is desirable to limit the magnitude of the write sense current so that the magnetic bit is not damaged by the current. During a read operation, it is desirable to reduce the resistance that is in series with the magneto-resistive bit to maximize the sensitivity to the resistance change of the GMR bits. Accordingly, it is contemplated that the switch may have at least two resistive modes including an intermediate resistive mode and a lower resistive mode. The intermediate resistance mode may provide a limiting resistance in series with the magneto-resistive bit to limit the amount of write sense current that is drawn from the word line during a write operation. The lower resistance mode may be used to reduce the resistance that is in series with the magneto-resistive bit during a read operation to maximize the sensitivity of the read operation.
When the switch includes a transistor, the intermediate resistive mode may be provided by operating the transistor in the saturation region, where the current flowing through the transistor is controlled by the voltage on the gate of the transistor. By providing an appropriate voltage to the gate of the transistor, the desired write sense current can be provided. The lower resistance mode may be provided by operating the transistor in the linear region, with the transistor fully turned on.
It is contemplated that the switch may also have a higher resistive mode for substantially preventing the write sense current and the read sense current from flowing from the word line. This higher resistance mode may allow the magneto-resistive bit to be deselected, which may be particularly important when multiple magneto-resistive bits are controlled by the same word line.
To provide a differential magneto-resistive output signal, it is contemplated that a magneto-resistive storage element may be provided that includes two magneto-resistive bits. In this illustrative embodiment, the word line may extend adjacent the first and second magneto-resistive bits. The word line may be connected to the first end of the first magneto-resistive bit and the first end of the second magneto-resistive bit. The word line preferably extends adjacent the first magneto-resistive bit in a first direction and adjacent the second magneto-resistive bit in a second opposite direction. This may provide a word line magnetic field component that extends toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit. Since the magnetization vector of the pinned layer of the first and second magneto-resistive bits preferably are in the same direction, this configuration causes the first and second magneto-resistive bits to be written into opposite magneto-resistive states.
As above, a switch is preferably coupled to the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit. The switch selectively provides a path for a write sense current and a read sense current to flow from the word line, through at least part of the first and second magneto-resistive bits, and to a predetermined voltage such as ground. The switch preferably has at least two resistive states including an intermediate resistive state and a lower resistive state.
During a write operation, a word line current is provided to the word line. The word line current provides a write magnetic field component toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit. When the switch is activated, the write sense current is drawn from the word line current and through the first and second magneto-resistive bits. This causes the first magneto-resistive bit to be written to a first resistive state and the second magneto-resistive bit to a second opposite resistive state.
During a read operation, the word line is preferably divided into a first word line and a second word line, with the first word line extending adjacent the first magneto-resistive bit and the second word line extending adjacent the second magneto-resistive bit. This may be accomplished by providing a word line switch between the first word line and the second word line. The word line switch may be activated to connect the first word line and the second word line during a write operation, and may be deactivated to effectively disconnect the first word line from the second word line during a read operation.
It is recognized that in some embodiments, a word line switch may not be needed. For example, the first word line and the second word line may always be separated, even during a write operation. In this embodiment, the word line current does not traverse from the first word line to the second word line. Instead, a first word line current may be provided to the first word line, and a second word line current may be provided to the second word line. The polarity of the first and second word line currents may then be adjusted so that the first magneto-resistive bit and the second magneto-resistive bit are written into opposite resistive states.
A read circuit is preferably coupled to the first word line and the second word line. The read circuit provides a path for a first read sense current to the first word fine and a second read sense current to the second word line. The first read sense current and the second read sense current are preferably substantially identical. The switch or switches in the magneto-resistive element are activated to draw the first read sense current through the first magneto-resistive bit and the second read sense current through the second magneto-resistive bit. The read circuit senses the resistive state of the magneto-resistive bits by sensing the difference between the first read sense current and the second read sense current, or the differential voltage at the first ends of the first and second magneto-resistive bits.
It is contemplated that the read circuit may include a latch circuit similar to that shown in co-pending U.S. patent application Ser. No. 09/059,871, filed Apr. 14, 1998, and entitled xe2x80x9cNON-VOLATILE STORAGE LATCHxe2x80x9d, U.S. patent application Ser. No. 09/396,189, filed Sep. 14, 1999 and entitled xe2x80x9cNON-VOLATILE STORAGE LATCHxe2x80x9d, and U.S. patent application Ser. No. 09/059,871, filed Apr. 14, 1998, and entitled xe2x80x9cNON-VOLATILE STORAGE LATCHxe2x80x9d, all of which are incorporated herein by reference. More specifically, the read circuit may include a latch circuit that includes a first inverter and a second inverter coupled together in a cross-coupled configuration. The latch circuit preferably also includes a load transistor coupled between the input terminals of the first and second inverters. The load transistor is used to load the state on the negative supply terminals of the first and second inverters into the latch circuit.
In accordance with this embodiment of the present invention, the first word line may be coupled to the negative supply terminal of the first inverter, and the second word line may be coupled to the negative supply terminal of the second inverter. The first end of the first magneto-resistive bit is preferably coupled to the negative supply terminal of the first inverter via the first word line, and the first end of the second magneto-resistive bit is preferably coupled to the negative supply terminal of the second inverter via the second word line. During a read operation, the second ends of the first and second magneto-resistive bits are preferably coupled to ground via a switch or the like, as described above.
In this configuration, when the load transistor of the read circuit is activated, identical sense line currents are provided to the first word line and the second word line via the negative supply terminals of the first and second inverters. With the switch enabled, the first and second read sense line currents pass through the first and second magneto-resistive bits, respectively. Since the first and second magneto-resistive bits are in opposite resistive states, the voltage at the negative supply terminals of the latch circuit is not equal. Thus, when the load transistor is deactivated, the latch circuit assumes the state that corresponds to the voltage differential between the negative supply terminals of the first and second inverters. This state corresponds to the resistive state of the magneto-resistive bits.